1. Field of the Invention
The present invention relates to the field of semiconductor devices and more specifically to patterning of an interlayer dielectric layer.
2. Discussion of Related Art
The fabrication of semiconductor devices with smaller dimensions and the increasing switching speeds of transistors necessitate the use of copper lines and low-k interlayer dielectric (ILD) layers to accommodate the high speed signals. The use of the copper and low-k interlayer dielectric layers reduces the resistance of the metal interconnects and the capacitance between the metal interconnects to enable the high speed signals to be transmitted. Because process techniques used to pattern layers within a layer stack used to fabricate a semiconductor device also effect any low-k Interlayer dielectric layer included in that layer stack, exposure to the other processes alter the low-k interlayer dielectric layer from the shape or characteristics the layer was designed to exhibit.
A current solution to protect a low-k interlayer dielectric layer is to form a hard mask layer over a low-k interlayer dielectric to protect the low-k interlayer dielectric layer from processes performed on other layers. For example, an anti-reflective layer and a photoresist layer may be formed over an interlayer dielectric layer for patterning the interlayer dielectric layer as necessary to form a semiconductor device. Once the low-k interlayer dielectric layer is patterned, the remaining photoresist and anti-reflective layer must be removed. In the absence of using a hard mask layer that separates the interlayer dielectric layer from the anti-reflective and the photoresist layers, a dry or wet etch process performed to remove an anti-reflective layer and a photoresist layer would result in degradation of the interlayer dielectric layer. As mentioned above, the degradation results because the chemistries that are used to etch or remove photoresist and anti-reflective layers may damage an ILD layer. Therefore, the characteristics or dimensions of the patterns in the ILD may be significantly altered during the etching or removal of an anti-reflective and photoresist layers. This ultimately would result in unreliable operation of semiconductor devices or low manufacturing yields of properly operating semiconductor devices. Therefore, the use of a hard mask is needed to protect the ILD layer from the processes used to alter other layers.
As the dimensions of the patterns implemented in the interlayer dielectric layer decrease, the photoresist layer begins to breakdown making forming critical dimensions unreliable. To increase the reliability of patterning smaller dimensions in the interlayer dielectric layer, a thicker hard mask is needed to maintain the fidelity of a pattern printed on a mask used for photolithography. However, the use of a thicker mask prevents the proper alignment of additional layers because the alignment marks are no longer as accessible. Because proper alignment is now more difficult, manufacturing yields of semiconductor devices degrade.
Another problem with the use of a hard mask is that the hard mask is designed to protect a lower interlayer dielectric layer from chemicals and processes used in the manufacturing process making the hard mask layer difficult to remove. One method of removing the hard mask is through chemical mechanical polishing (CMP) after the deposition of an interconnect metal. Leaving the hard mask over the interlayer dielectric until after the deposition of an interconnect metal allows the interlayer dielectric layer exposed to intermediary processes that result in the interlayer dielectric layer undercutting the hard mask layer. The interlayer dielectric layer undercutting the hard mask layer during intermediary processes results in the formation of voids in metal deposited in a trench or via formed in the interlayer dielectric layer. The voids in the interconnect results in unreliable operating characteristics and performance of a semiconductor device and decreases the reliability of the semiconductor device.